1. Field of The Invention
The present invention relates to a semiconductor integrated circuit device, a clock sync control method and a data transfer control method, which are provided for reducing power consumption of an internal module connected to a bus. More specifically, the present invention relates to a semiconductor integrated circuit device, a clock sync control method and a data transfer control method, which control the operating frequency of the internal module and the internal bus, and attain reduction of power consumption by controlling a clock and a clock sync signal.
2. Description of the Related Art
In recent years, with the development of high-speed, large-scale semiconductor processors, how to reduce the power consumption of the semiconductor processors has come to be the important subject.
As the method for reduction of power consumption of a semiconductor integrated circuit device, several measures have been taken by the conventional technology, which follows: 1) when the fast operation of the processor is unnecessary, the clock frequency is reduced dynamically; 2) the clocks with the operating frequencies according to the demands are respectively supplied to the internal modules within the processor; 3) the supply of the clock to the unnecessary module is stopped (which is controlled with the register, etc.); and 4) the power of the clock tree is reduced by using the gated clock.
The main power consumption factor P of a semiconductor processor is represented by the formula:P=C×V^2×F
(C: load capacity, V: source power voltage, F: operating frequency)
The above-mentioned methods are to reduce the power consumption by paying attention to the operating frequency F (or the switching probability of load capacity) in this formula.
There are many methods of attaining reduction of power consumption by controlling the source power voltage V. In recent years, however, the method of controlling the clock supply to the neighboring modules of which operation is not demanded attracts the attention.
Japanese Laid-Open Patent Application No. 2002-328744 discloses a device for preventing the deviation of clock synchronization to perform the data transfer between the modules when switching the clock frequency, as the conventional technology relevant to the present invention.
Japanese Laid-Open Patent Application No. 2003-58271 discloses a device and method for preventing the occurrence of the hang-up at the time of switching the clock frequency or shifting to the power down mode.
Japanese Laid-Open Patent Application No. 6-202754 discloses a device and method of carrying out the power down on the basis of the functional unit (module) of an integrated circuit. The state of each module is monitored, and, when the operation of the module is found unnecessary, the supply of the clock to the module is stopped.
Japanese Laid-Open Patent Application No. 8-194663 discloses a method of activating or deactivating the clock line characteristics for computer system and its peripheral bus. In this method, a command register for clock control is provided, and the clock control is carried out by stopping the supply of the clock to the module the operation of which is not needed.
Japanese Laid-Open Patent Application No. 2000-35886 discloses a method of attaining the synchronization of respective clocks using the latch when performing the signal switching between the respective modules which are operated in a case in which the ratio of the corresponding clocks is not an integral multiple.